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學校名稱輔仁大學
系所名稱電子工程學系
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學號487506065
研究生(中)史振生
研究生(英)Jen-Sheng Shih
論文名稱(中)現場可規劃邏輯陣列測試與診斷技術之研究
論文名稱(英)Built-In Self-Test and Fault Diagnosis for Lookup Table FPGA's
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指導教授(中)呂學坤
指導教授(英)Shyue-Kung Lu
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學位類別碩士
畢業學年度88
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關鍵字(中)現場可規劃邏輯陣列 可規劃邏輯區塊
關鍵字(英)FPGA CLB
摘要(中)隨著超大型積體電路輔助設計技術的進步,在硬體設計中,由於現場可規劃邏輯陣列 (FPGA) 具有低製造成本、可控制性、模擬成本低與製作速度快,因此使用情形日益普遍。一般現場可規劃邏輯陣列包含有可結構化邏輯區塊(CLBs)、輸入輸出區塊 (IOBs) 和可程式化的連線資源。 這篇論文裡,我們提出兩種獨特的測試方法來測試現場可規劃邏輯陣列內部的可結構化邏輯區塊陣列,此兩種方法分別為 ILA-based 和 hybrid 之測試方法,但在使用本論的方法之前提必須假設可結構化邏輯區塊為一般 Xilinx 的結構。在 ILA-based 方法中,我們定義 cell 是由一個縱列k個鄰近可結構化邏輯區塊所組成的,每一個可結構化邏輯區塊有 k 條輸入線且它們的輸入線是一致的,而 hybrid 方法則是透過連線將單一個可結構化邏輯區塊規劃成 scell。經由定義新的 cell 或 scell 架構,再將每個cell (scell) 結構化為bijective功能使 cell (scell) 可以應用於M-testable。在每個結構化中,把最少完全輸入序列輸入 2k 於每一個線陣列的最左邊的 cell (scell),我們可以從最右邊的 cell (scell) 觀察其輸出結果。在新的結構,我們簡化了現場可規劃邏輯陣列原本的結構而變成一維的線陣列,若要使錯誤的涵蓋率 (fault coverage) 達到100%,則需要 k+2 次的結構化次數。在內建自我測試結構中,我們需要用兩個程序的 k+2 次的結構化次數,而做 Fault Diagnosis 則依兩種方法而有不一樣的程序次數。最後我們可以從驗證中看出我們所花的測試向量與測試結構化是最少的數目。 從推導的方程式中,我們可以看出錯誤診斷分析程序時間的複雜度與現場可規劃邏輯陣列的大小無關,因此我們可以稱我們的方法能使現場可規劃邏輯陣列為C-diagnosable。
摘要(英)Along with the progress of VLSI manufacturing technology, Field Programmable Logic Arrays (FPGA) are widely used for hardware prototyping. Because of their shorter turn-around, low manufacturing cost and programmability, they are widely adopted for a variety of VLSI designers. An FPGA usually consists of an array of identical configurable logic blocks (CLBs), programmable I/O blocks (IOBs), and programmable interconnects. Two novel approaches, the ILA-based and the hybrid methods, to testing lookup table (LUT) based field programmable gate arrays are proposed in this thesis. A general structure for the basic configurable logic array blocks is assumed. For the ILA-based approach, we group k CLBs in the column into a cell, where k denotes the number of inputs of an LUT. In the hybrid method, we configure the interconnect resources to modify the CLBs into scells. The whole chip is configured as a group of one-dimensional iterative logic arrays of cells (scells). We assume that in each linear cell array, there is at most one faulty cell (scell), and multiple faulty CLBs in the same cell (scell) can be detected. For the LUT, a fault may occur at the memory matrix, decoder, input or output lines. The switch stuck-on and stuck-off fault models are adopted for multiplexers. New conditions for C-testability of programmable / reconfigurable arrays are also derived. Our idea is to configure the cells (scells) to make their function bijective and this property is helpful for applying pseudoexhaustive test patterns (a minimal complete input sequence) to each cell (scell) and propagating errors to the observable outputs. In order to detect all the faults defined, k + 2 configurations are required and the resulted number of test patterns is 2k. A novel built-in self-test structure is also proposed in this paper. The input patterns can be easily generated with a k-bit counter. The number of configurations for our BIST structures is 2k + 4. Our BIST approaches also have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty cell (scell), three test sessions are required. However, the maximum number of configurations is 2k + 4 for diagnosing a faulty cell (scell). Experimental results show that our approaches require less numbers of test patterns and test configurations. Moreover, the diagnosis complexity is independent of the array size of an FPGA. Therefore, C-diagnosability is achieved with our approaches.
論文目次中文摘要 …………………………………………………………… i 英文摘要 …………………………………………………………… ii 誌謝 ………………………………………………………………… iv 目錄 ………………………………………………………………… v 圖目錄 ……………………………………………………………… vii 表目錄 ……………………………………………………………… ix 關鍵字 ……………………………………………………………… 1 第一章 緒論 ……………………………………………………… 2 1.1 研究動機 …………………………………………………2 1.2 研究方向 …………………………………………………3 1.3 本文內容 …………………………………………………4 第二章 現場可規劃邏輯陣列之架構 ………………………….. 5 第三章 測試理論 ………………………………………………….8 3.1 M-可測試性定理 ……..………………………………….8 3.2 連續性邏輯陣列測試方法 ……………………………. 9 3.3 混合式之測試方法 …………………………………….. 17 第四章 內建自我測試 ……………………………………………23 4.1 連續性邏輯陣列之BIST內建自我測試 ………………23 4.2 混合式之內建自我測試 ………………………………. 25 第五章 錯誤診斷 ……………………………………………….. 28 5.1 連續性邏輯陣列之Fault Diagnosis ……………….……28 5.2 混合式之Fault Diagnosis ……………………………… 30 第六章 驗證結果與比較 ……...…………………………………32 6.1 連續性邏輯陣列之驗證 ………………………………..32 6.2 混合式之驗證 …………………………………….…….34 6.3 複雜度的比較 …………………………………………..37 6.4 其他工作的比較 ……………………………………..41 第七章 結論 …………………………………………………….43 7.1 本論文之特色 …………………………………………43 7.2 未來發展 ………………………………………………44 已發表之研討會論文 ……………………………………………...48
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